The present invention relates to residue-checking a floating point unit (FPU) of a microprocessor, and more specifically, to distributed residue-checking of an FPU while power-saving data flow elements within the FPU.
A conventional FPU of a microprocessor typically includes a residue checking apparatus which performs residue checking for detecting errors in arithmetic floating-point operations such as addition, subtraction, multiplication, division, square root or convert operations. The residue checking is performed within a checking flow by performing the same operations on the residue as those performed on the operands of the FPU. That is, a checking flow is performed in parallel to a data flow within the FPU. In FIG. 1, a data flow 1 and a checking flow 2 of a conventional residue checking apparatus for a FPU is shown. Operands A, B and C are provided by an input register 3 in the data flow 1. The operands A, B and C are processed differently based on different functional elements 4 e.g., an aligner 21 and a normalizer 22, and a result is provided by a result register 5. Residues are generated at specified positions within the data flow 1 by residue generators 6. Modulo decoders 7 are connected to the residue generators 6 and provide residue modulos to different functional elements 8 such as a modulo multiplier 16, modulo adder 17, modulo subtract 18, modulo multiplier 19, and modulo subtract 20 within the checking flow 2. In the first stage 10 of the checking flow 2, the residue modulos of operands A and B are multiplied by the modulo multiplier 16. In the second stage 11, the residue modulo from operand B is added to the product-residue modulo from stage 10 via the modulo adder 17. In the third stage 12, the residue modulo of bits lost at the aligner 21 is subtracted by the modulo subtract 18 from the sum of the second stage 11. In the fourth stage 13, residue multiplication with a constant to compensate for normalized-shift is performed by the modulo multiplier 19. Then, in the fifth stage 14, a residue-subtract of bits lost at the normalizer 22 is performed by the modulo subtract 20. In the sixth stage 15, a single check operation is performed by a compare element 9. The compare element 9 compares the result provided by the modulo subtract 20 with the residue modulo of the result provided by the result register 5 of the data flow 1.
Power consumption of microprocessors is an important concern. FPUs consume a notable amount of power of the microprocessors. Therefore, power-saving techniques are employed to reduce the amount of power consumed by the FPUs within the microprocessors. Several problems occur in the conventional residue checking apparatus when power-saving techniques are employed. For example, since a single check is performed as shown in FIG. 1, the conventional residue checking apparatus is inoperable while power saving for some of the data flow elements by temporarily turning off their clocking. The single check also needs to be disabled completely in case of timing problems of the checking circuitry. In addition, a point of failure may not be identified, and the conventional residue checking apparatus may not be usable for complex operations within a multi-cycle pass such as divide, square root, and extended precision operations.